As is known, and as is illustrated schematically in FIG. 1, a non-volatile memory device, designated as a whole by 1, for example of a flash type, generally comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows (word lines, WL), and columns (bit lines, BL). The memory array 2 is further in general divided into a plurality of sectors, each comprising respective word lines and bit lines.
Each memory cell 3 is constituted by a storage element, for example formed by a floating-gate transistor, with a gate terminal designed to be connected to a respective word line WL, a first conduction terminal (in particular the drain terminal) that is designed to be coupled to a respective bit line BL, and a second conduction terminal (in particular, the source terminal) that is connected to a reference-potential line (defined as source line, SL). The gate and source terminals of the memory cells 3 of a same word line WL are further electrically connected to one another.
A column-decoder circuit 4 and a row-decoder circuit 5 enable selection, on the basis of address signals received at the input (generated in a per se known manner and designated as a whole by Add), of memory cells 3, and in particular of the corresponding word lines WL and bit lines BL, each time selected, enabling biasing thereof at appropriate voltage and current values during memory operations.
The column-decoder circuit 4, in particular, provides a read path, designed to create a conductive path between the bit lines BL of the memory array 2 each time selected and a sense-amplifier circuit 10, which is designed to compare the current circulating in the addressed memory cell 3 to be read (the so-called direct memory cell), with a reference current in order to determine the value of the datum stored. This reference current may be generated by an appropriate current generator, in the case of so-called single-ended reading, or else by a reference memory cell (the so-called complementary memory cell), associated to a respective reference or complementary bit line BL′, physically or logically adjacent in the same memory array 2, in the case of a so-called differential reading.
It is known, for example, that verify operations, subsequent to programming operations, envisage reading of a single-ended type of the data that have been programmed in the memory cells, whereas operations of effective reading of the data stored generally envisage reading of a differential type.